The invention relates to a CMOS integrated circuit comprising a semiconductor body with a layer-shaped region of substantially a first conductivity type adjoining a surface, in which region an electric circuit is provided having at least two adjacent circuit blocks separated from one another by an intermediate region and formed in particular but not exclusively by rows of standard cells, which circuit blocks are built up from MOS transistors having a channel of the second conductivity type and provided in the layer-shaped region of the first conductivity type and from MOS transistors having a channel of the first conductivity type and provided in surface regions of the second conductivity type, called first surface regions hereinafter, while the surface is covered with an electrically insulating layer on which a wiring pattern is provided comprising a supply line and one or several signal lines provided above the intermediate region.
An integrated circuit realised with standard cells is described inter alia in the book "Geintegreerde MOS-schakelingen, een inleiding tot VLSI en ASIC's" (Integrated MOS Circuits, an Introduction to VLSI and ASICs) by H. Veendrick, (1990) Delta Press BV, Amerongen, the Netherlands, in particular pp. 376-77. The standard cells may have various kinds of logic gates which may all have the same height. The cells are arranged in rows which are mutually separated by transistorless interspacings which are used as wiring channels. In the wiring channels, conductor tracks are formed which interconnect the cells so as to guide signals from one cell to another cell. The width of the wiring channels may vary in dependence on the quantity of wiring. The supply lines are usually laid immediately above the cells, but sometimes they are provided in the wiring channels.
Noise superimposed on the supply may form a major problem in large integrated circuits. This noise may be caused, for example, by switching of certain elements, for example flipflops, in particular when more elements switch simultaneously, whereby locally considerable currents and thus high voltage peaks occur in the supply lines. Another source of noise may be formed by heavily loaded output stages. The peak currents in the supply may cause voltage changes in the circuit which adversely affect parameters such as, for example, speed and reliability. Canadian Patent 1,204,511 proposes to reduce supply noise by means of decoupling capacitances which are formed by a local capacitor consisting of a reverse-biased pn junction which is connected to the supply. This capacitor requires additional space so that the crystal becomes larger and the circuit accordingly becomes more expensive. In addition, it is often desirable to lay the decoupling capacitor even closer to the elements causing the said current peaks than in this known circuit.
It will be clear that the problems described above will not occur in standard cells only. The present invention offers a solution to these problems in circuits which are built up in blocks, which blocks comprising circuit portions are provided in a more or less regular pattern on the chip, mutually separated by routing channels.